The usage of low voltage power supplies where appropriate can effectively reduce overall power consumption in an electronic circuit. Parts of the circuit that require a higher voltage can use a higher voltage supply, and parts of the circuit that can operate using a lower voltage supply can use the lower voltage supply thus using less power.
FIG. 1 illustrates a circuit 100 comprising a conventional inverter combined with a level shifter. The circuit 100 comprises a PMOS 101 (P1) and a first NMOS 102 (N1) and a second NMOS 103 (N2) coupled between an input signal 104 (IN) and an output signal 105 (OUT) of the circuit 100. An input unregulated power supply voltage 106 (vccio) is coupled to the PMOS 101 to drive the circuit 100. A regulated power supply voltage 107 (vpwr) is supplied to the NMOS 102 (N1). The source of NMOS 103 is maintained at a ground potential. In the circuit described above the input trip point is set by the ratio of P1 and N1 with respect to N2, i.e. (P1 and N1):N2. A disadvantage of the circuitry 100 is that the input trip point is a fixed percentage of the supply voltage level (vccio) across the power supply voltage range. The input trip point can be varied across the supply voltage range by adding switched transistors, for example pull-up transistor and/or pull-down transistors, in parallel with the PMOS 101 and NMOS 102, wherein control signals input to the circuit are required to configure the switched transistors. The input trip point of conventional circuit 100 cannot dynamically adapt to the power supply voltage range.
FIG. 2 illustrates another input buffer circuit 200. The input buffer circuit 200 comprises a plurality of input stages, for example three independent input stages, a first input stage 201, a second input stage 202 and a third input stage 203. For example, each of these pluralities of input stages 201, 202 and 203 comprises NOR gates depicted as nor1, nor2 and nor3. The input trip points of each of the input stages 201, 202 and 203 are typically optimized for a specific power supply voltage range for the circuit 200. The plurality of input stages 201, 202 and 203 are coupled to a fourth NOR gate 208. A NMOS 206 (N1) is coupled to the third input stage 203 and to a regulated power supply voltage Vpwr 207. The plurality of input stages 201, 202, and 203 and other components 208 and 206 are coupled to form a circuit which is supplied with an input signal 204 (in) and produces an output signal 205 (out).
Control signals en1_n, en2_n and en3_n are provided to respective input stages 201, 202 and 203, and the control signals en1_n, en2_n and en3_n are used to select which of the input stages 201, 202 or 203 is in an active state. Only one of the control signals from en1_n, en2_n and en3_n can be in an active state at a given instant of time, for example an instant where the circuit is at logic 0. During this instant of time, one of more of the input stages from 201, 202 and 203, for example 203 (NOR3) may be powered from a low voltage supply (LV) and may be constructed at least partially with LV transistors. The output signal 205 (out) level translation from the vccio supply (HV), a high voltage supply, to the vpwr (LV) supply is incorporated in a combination of the gates.
A disadvantage of the circuit 200 is that multiple input stages are used; one stage for each range of available input trip points, which causes the circuit 200 to have a higher input load capacitance, a higher standby current and requires a larger chip area. A further disadvantage of the circuit 200 is that the selection of the input buffer stages for the desired input trip point requires an external control input signal as the input trip points cannot dynamically adapt to the power supply voltage range.
It would therefore be desirable to have an improved circuit, preferably a circuit that dynamically adapts to power supply voltage ranges, and has a high reliability.